I2C Description

The IS3720 operates as a slave in the I2C-serial interface. It supports Standard Mode (100 kHz), Fast Mode (400 kHz), and Fast Mode Plus (1 MHz). The I2C‑master device, typically a microcontroller or a microprocessor, initiates and manages all read operations to the slave.

The IS3720 is represented on the bus by the I2C device address: 22.

Pull-up resistors are required on the SCL and SDA lines for proper operation. The resistor values depend on the bus capacitance and operating speed. Typical values are 4.7 kΩ for Standard Mode (100 kHz) and 2 kΩ for Fast Mode and Fast Mode Plus (400 kHz and 1 MHz).

The IS3720's I2C pins high state can be either 3.3 V or 5 V. A logical '0' is transmitted by pulling the line low, while a logical '1' is transmitted by releasing the line, allowing it to be pulled high by the pull-up resistor. The Master controls the Serial Clock (SCL) line, which generates the synchronous clock used by the Serial Data (SDA) line to transmit data.

A Start or Stop condition occurs when the SDA line changes during the High period of the SCL line. Data on the SDA line must be 8 bits long and is transmitted Most Significant Bit First and Most Significant Byte First. After the 8 data bits, the receiver must respond with either an acknowledge (ACK) or a no-acknowledge (NACK) bit during the ninth clock cycle, which is generated by the master. To keep the bus in an idle state, both the SCL and SDA lines must be released to the High state.

The memory map consists of 632 registers; therefore, addressing a register requires 2 bytes. Each register is 8 bits wide.

The IS3720 requires clock stretching.

The operability of the Read and Write commands of the IS3720 is very similar to an EEPROM memory. Thinking of the IS3720 as an EEPROM memory is a good analogy to quickly understand how to communicate with the device.

Highlights

I2C Device Address: 22

I2C Memory Map Addressing Size: 16-bit (2x 8-bit)

I2C Memory Map Register Size: 8-bit

Compatible I2C Speeds:

• Standard Mode (100 kHz), recommended SCL and SDA pull-up value: 4.7 kΩ
• Fast Mode (400 kHz), recommended SCL and SDA pull-up value: 2 kΩ
• Fast Mode (10 MHz), recommended SCL and SDA pull-up value: 2 kΩ

Supported Operations:

• Single-Byte Write
• Multiple-Byte Write (up to 632 registers)
• Single-Byte Read
• Multiple-Byte Read (up to 632 registers)

Overreading and Overwriting the memory:

• If a write operation starts at a valid memory address (0 to 631) and continues past the last valid address, it will roll over to address 0.
• Starting a write operation to an invalid memory address (greater than 631) will result in a NACK and data will be discarded.
• If a read operation starts at a valid memory address (0 to 631) and continues past the last valid address, it will roll over to address 0.
• Starting a read operation at an invalid memory address (greater than 631) will return a value of 0xFF.